CASPA summit: chip-to-chip interconnect eats 60-70% of package energy, AI chip design targets 9-month cycles
ai · x · 2026-10-25
Takeaways from Day 2 of CASPA CEO Summit panels:
Hardware
- Compute is no longer the bottleneck — data movement is: chip-to-chip interconnect can consume 60-70% of a package's energy
- Memory has shifted from commodity to strategic; every idle GPU waiting on data burns money
- Fab boom ahead: 78 of 102 fabs coming online by 2029 are in Asia, and SEMI forecasts 50+ additional fabs needed through 2035
Chip design
- Models change in weeks while chips take 18-24 months; the industry goal is cutting that to 9 months
- Key claim: agentic harnesses alone won't get us there — EDA engines themselves must get faster instead of leaning on legacy EDA
- RL for chip design is stuck on tooling: one run takes a day, and practitioners are begging for faster tools
Related event: CASPA Summit: Interconnect Energy Emerges as AI Chip Bottleneck(2 posts)→
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