CASPA Summit: Interconnect Energy Emerges as AI Chip Bottleneck

At the CASPA CEO Summit in Santa Clara, panelists noted semiconductors are regaining venture capital attention. Discussions highlighted that data movement, not compute, is the bottleneck, with interconnects consuming 60-70% of package energy, and called for AI chip design cycles to shrink from 24 to 9 months.

2026-10-24 ~ 2026-10-25 · 2 related posts

• Semis roar back into VC focus as CASPA panel calls for 1000x faster, greener AI chips — hardimanjames · 2026-10-24
• CASPA summit: chip-to-chip interconnect eats 60-70% of package energy, AI chip design targets 9-month cycles — ai · 2026-10-25