Hands-on test of Harmonic's Aristotle: Verilog proof works but artifacts questioned

On October 29, researcher thomasahle shared a series of posts documenting his experience using Harmonic's math theorem-proving model and its formal verification system, Aristotle, to verify a hardware design — a roughly 200-line Verilog floating-point division file (FPDivide.v / fpdiv, later confirmed as IEEE-754 FP32 single precision; the user's initial mention of FP64 was a typo).

Confirmed

• Aristotle successfully proved two of the circuit's specified properties: confirming that the ports are 32-bit single precision, and establishing properties such as "bit 23 of the quotient register is set" and "for normal inputs, the division result is bitwise correct with round-toward-zero."
• Beyond formal verification, the simulation stage uncovered 5 additional classes of floating-point bugs.
• The Agent features multi-turn clarifying-question design: for example, during verification it proactively pointed out that a combinational always block was not assigned on all control paths and asked the user for clarification, which thomasahle praised.

Unconfirmed

• The root cause of the lag and queuing issues (task scheduling, compute limits, or product policy) was never explained by Harmonic; thomasahle only learned that one project can run at a time.

Why it matters

This was an end-to-end real-world test of "LLM + formal methods" for verifying actual hardware designs: on the proof side, it delivered a passing grade (correctness properties held, and simulation even caught defects), but the engineering experience fell noticeably short — thomasahle complained that reading 200 lines of code took 27 minutes while stuck in a "working" state with no progress or thinking indicators, the task queue wait was 10 minutes, and concurrent tasks were limited (the system prompted "too many tasks in progress or waiting to start; wait for one to finish or stop one before trying again"). For developers hoping to bring such Agents into everyday chip verification workflows, throughput and observability are the next problems that must be solved.

2026-10-29 ~ 2026-10-29 · 6 related posts

• Testing Harmonic's math agent: it asks sharp clarifying questions to formally verify Verilog — thomasahle · 2026-10-29
• Harmonic's agent limits concurrent tasks, users hit long queues in early testing — thomasahle · 2026-10-29
• Aristotle agent stalls for ages on a 200-line Verilog file with no progress signal — thomasahle · 2026-10-29
• [source] Harmonic's math model formally proves FP division properties of a 200-line Verilog file — thomasahle · 2026-10-29
• [source] Harmonic's Aristotle formally proves fpdiv circuit, then simulation finds 5 IEEE-754 bugs — thomasahle · 2026-10-29
• [source] Harmonic's circuit proofs lack verifiable artifacts; Claude could do it for far less than $63 — thomasahle · 2026-10-29