Harmonic's Aristotle formally proves fpdiv circuit, then simulation finds 5 IEEE-754 bugs
thomasahle · x · 2026-10-29
Screenshots of a session with Harmonic's formal verification system Aristotle show it successfully proving two agreed properties of an fpdiv (IEEE-754 FP32 division) circuit: 32-bit ports (FP64 was a typo), normal finite operands, quotient truncated toward zero to 24 significant bits, plus RTL properties on the combinational always block.
Notably, after completing the proof, Aristotle ran simulations on cases outside the agreed scope and surfaced what look like real bugs:
- Negative infinity treated as NaN (-∞/1.0 returns NaN instead of -∞)
- Division by negative zero missed (1.0/(-0.0) gives a finite value, not -∞)
- Zero results always +0 (-1.0/+∞ doesn't yield -0)
- Exponent overflow/underflow wraps around; subnormals unhandled
- Truncation instead of IEEE round-to-nearest-even (1.0/3.0 off by 1 ulp)
The author also raises an interesting question: since simulation is far faster, why not simulate first and prove afterwards?
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