Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation
Seongwon Yoon, Pin-Jun Chen, Shimeng Yu
cs.AR
2026-08-25
Cross-layer simulation finds ~47ms thermal-tuning stalls on wafer-scale MoE optical links; dropping them yields 2.7x/3.8x/3.3x on Mixtral, Qwen-MoE, and LLaMA-MoE.
Every MoE block ships tokens to the accelerators that host the chosen experts, then gathers the results. Those two all-to-all phases can take one-third to more than half of an iteration, and routing is skewed: a few experts stay hot, so traffic and heat pile up on the same devices.
Wafer-scale silicon photonics can stack bandwidth with dense wavelength-division multiplexing (DWDM), targeting 1.5 TB/s die-to-die, in the Tesla Dojo class. The microring resonator (MRR) is what cuts effective throughput. It is smaller than 50 μm and a natural wavelength filter, but it stays aligned only inside a sub-1 K window. Mach-Zehnder and electro-absorption devices tolerate more than 50 K. The usual fix is thermo-optic tuning: heat the waveguide until the resonance sits on the carrier. That takes microseconds to milliseconds and needs a live control loop. When a GPU compute pulse dumps heat into the photonic layer, the rings drift and the link has to pause while they lock again.
Georgia Tech wires workload, package thermals, devices, and a packet-level network into one chain. Stall time comes out of the thermal model; it is not an assumed constant.
The system is a 300 mm wafer with a 4×4 GPU array in the center and 16 HBM reticles on the rim. Each reticle stacks GPU, electrical IC (EIC), and photonic IC (PIC), then bonds onto a silicon-nitride waveguide interposer. Each wavelength runs at 32 Gb/s, 32 wavelengths share a waveguide, and 12 waveguides give 12.288 Tb/s. There is no on-wafer optical switch. Intermediate reticles regenerate with an optical-electrical-optical hop.
Thermal boundary conditions and materials come from Coenen et al.'s 2.5D/3D co-packaged-optics characterization. Peak XPU power is 700 W; cooling is only the top-side microchannel cold plate. The power trace is built from a FlexFlow task graph, not a measured wall-power log: attention and expert GEMMs get 700 W, the gate 40% (280 W), add-and-norm 20% (140 W), and all-to-all 12% board-idle (84 W) because those operators launch no compute kernel. Each all-to-all event is fixed at 350 ms on the timeline.
Temperature is then turned into a stall in four steps. A silicon-ring coefficient of 80 pm/K converts T(t) into resonance shift. A controller with a 0.0625 K/ms slew limit tracks that shift. Any interval where residual detuning exceeds 10% of the resonance FWHM (19.4 pm, about 1 dB extra loss) counts as a stall. The alternative is a lithium-niobate waveguide with an HZO ferroelectric gate: an electric field changes the index via the Pockels effect, and the polarization stays after the field is removed. Device-level switching is 5.4 ns, saturating near 10 ns. HZO keeps more than 85% of its polarization at 90°C.
Compute is profiled on H100, then mapped onto a hypothetical wafer system: Mixtral 8×7B on 256 GPUs / 16 wafers, Qwen-MoE 14.3B on 512 / 32, LLaMA-MoE 6.7B on 128 / 8.
Peak PIC cooling rates are about 0.18 K/ms for Mixtral and Qwen, 0.21 K/ms for LLaMA-MoE, against a 0.0625 K/ms thermo-optic tracker. Every iteration peak overshoots the optical budget. Steady-state mean stalls, and the iteration-time multiplier once those stalls are injected once per all-to-all round:
| Model | Expert-parallel degree | Mean stall | Iteration time vs stall-free |
| Mixtral 8×7B | EP 8 | 48.7 ms | 2.7× |
| Qwen-MoE 14.3B | EP 64 | 46.8 ms | 3.8× |
| LLaMA-MoE 6.7B | EP 16 | 47.4 ms | 3.3× |
The slowdown tracks EP degree, not stall length. Qwen has the shortest stall and the worst hit, because experts are spread across more peers. Below about 10 ms the extra delay is barely visible; past that it sits on the communication critical path.
With stalls removed, the photonic wafer is not a guaranteed win over electrical fabrics. On four-layer proxies at 400 Gbps per link, LLaMA-MoE finishes in 422.5 ms versus 732.0 ms on an electrical fat-tree and 486.9 ms on a flat NVLink-style mesh. Mixtral's 1089.5 ms is slower than the flat fabric's 843.9 ms. The 2.7-3.8× headline is the cost of thermal stalls on this design, not a blanket optical-versus-electrical claim.
At full layer count the mean stall grows to 173.9 ms (Mixtral), 68.3 ms (Qwen), and 96.9 ms (LLaMA-MoE). Packet-level simulation did not finish at that scale (50 minutes to 4.7 hours), so the 2.7 / 3.8 / 3.3 multipliers stay four-layer-proxy numbers. A sweep of Q, detuning budget, and tracker rate puts the reported mean stalls at the low end of the range, which makes the multipliers closer to conservative than optimistic.
Ferroelectric tuning is modeled as negligible latency. Stall windows imply 3.0 to 5.9 polarization switches per iteration. A 1 million-iteration run needs about 3-6 million cycles, still under the 10 million cycles reported for HZO at 125°C.
This is a quantitative warning for optical scale-up fabrics and MoE systems: stacking DWDM past 1 TB/s does not buy you out of a 47 ms lock time. Training alternates compute heat with communication bursts, and a thermo-optic loop cannot track the fastest transients. A non-volatile ferroelectric tuner moves the problem from milliseconds to nanoseconds, if the device survives millions of cycles next to a GPU.
The paper does not ship a product link. If Lightmatter, Celestial AI, or TSMC COUPE keep thermo-optic microrings, MoE-style compute/communicate alternation will tax effective throughput. For clusters already training Mixtral or Qwen-MoE, there is no knob to turn today. The claim is about the next scale-up optical package: treat tuning latency as a first-class constraint.
The network study uses a four-layer proxy (32 layers for Mixtral and LLaMA-MoE, 24 for Qwen). Full-depth packet simulation never finished, so the end-to-end multipliers do not close at full model depth. Power fractions are a roofline argument; the paper states there is no measured GPU power trace for this workload. The 350 ms all-to-all duration is an input, not an output of the optical network.
Ferroelectric evidence is TCAD plus Lumerical, plus cited HZO switching and endurance numbers. There is no fabricated transceiver dropped into the same network sim. Without stalls, the wafer design loses to a flat all-to-all fabric on Mixtral and Qwen. The large speedups come from removing a stall this architecture introduces.
H100 compute shapes are transplanted onto a 3D wafer stack that does not exist, so thermal time constants may not transfer. The physical constants are still literature point values, not measurements on this package. MixNet is compared only for Mixtral at EP 8; Qwen and LLaMA-MoE sit outside that public implementation's supported range.