Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI
Architect Labs
cs.AR, cs.AI
2026-08-27
From a two-architect spec, AI generated Redwood in two weeks. Qwen3-0.6B runs 12.1 tok/s on FPGA; Samsung 8nm projection is 49 tok/s at 1.335W, 3.4x Jetson Orin Nano perf/watt.
Chip programs still commit architecture years before volume silicon. The models they are supposed to run change in months. Teams pay twice: once for the generality they add as a hedge, and again when a new workload maps poorly onto frozen silicon. EDA vendors now advertise order-of-magnitude AI speedups on RTL, verification, and debug, including claims of compressing multi-month work into days. The 2024 Wilson report still has first-silicon success at 14%, the lowest in two decades, with 75% of IC/ASIC projects behind schedule. Task-level acceleration has not shown up as end-to-end program acceleration.
Public AI-generated chips have mostly been toy RISC-V cores or hardened numeric datapaths, almost never burned onto physical hardware running a modern model. Redwood is an attempt to collapse the stack: one spec, one objective, architecture through kernels generated together.
Architect Labs in Palo Alto built ALP, an in-house platform for end-to-end chip design. Two human architects wrote a high-level spec covering the workload and architectural constraints. Below that spec, the system generated the performance model, RTL, UVM environments, formal proofs, firmware, drivers, and custom kernels with no further human intervention. The appendix lists about thirty contributors; the two-architects claim covers the spec layer. ALP, in-house models, agent harnesses, and AI-native EDA tools already existed. From scratch means no pre-existing accelerator IP, not a design flow invented in those two weeks.
Redwood is a tile-based spatial-dataflow accelerator aimed at single-batch, low-power, ultra-low-latency inference for physical AI. The evaluated configuration, Redwood Nano, is a 2x2 tile array on an AMD Versal VPK180 FPGA at 250 MHz. Each tile splits a lean RISC-V control core (CRV) in the front end from transformer-specific engines in the back end: systolic GEMM/GEMV on integer MAC arrays, and a multi-lane SIMD unit for elementwise ops, reductions, and LUTs. Softmax uses the emulated algorithm from FlashAttention-4 so it reuses SIMD instead of a large dedicated block. Each tile has 512 KB of local SRAM.
The split lets sparse control run on a slower clock, and the front end can power down during kernel execution. The CRV hands a task list to a Core Task Manager and can idle; the CTM tracks out-of-order completions with task IDs, fencing, and looping. On-chip messages between tiles and DMA engines move scheduling into software. A host loads Dispatch Programs and kernels into tightly coupled instruction memory, the MCU programs routing tables and DMA, then fires kernels by ID. FlashAttention is a loop of tile launches over KV blocks and heads.
The design closed in two weeks: spec to RTL, verification, firmware, custom kernels, and timing closure, with 95% code and functional coverage on every block. A third week brought Qwen3-0.6B up on the FPGA. Architectural changes during that window were regenerated, reverified, and redeployed to hardware in under 48 hours. The repo peaked at 115 merge commits in a single day. The first RTL drop from simulation to FPGA found zero bugs.
FPGA measurements and the ASIC projection are different numbers.
Qwen3-0.6B decode, average over 128 generated tokens:
| Platform | Throughput | Clock | Bandwidth | Power |
| Redwood Nano FPGA | 12.1 tok/s | 250 MHz | 16 GB/s LPDDR4 | board power not reported |
| Jetson Orin Nano (measured) | 28 tok/s | 1020 MHz | 68 GB/s LPDDR5 | 2.59 W CPU+GPU |
| Redwood 8nm projection | 49 tok/s | 1 GHz | assumed same-class bandwidth | 1.335 W |
The FPGA runs at 12.1 tok/s average, 13 peak, slower than Jetson's 28. At 250 MHz, 16 GB/s, and 2x2 tiles, the roofline is 21.73 tok/s even if every operator hits its bound. One decoder layer is 1.241 ms of architectural latency; 28 layers are 34.76 ms; embedding, final norm, LM head, and argmax add 11.26 ms, for 46.02 ms per token. Memory service time is 3.6x arithmetic service time. If memory and compute are forced to serialize inside every operator, the conservative bound falls to 17.56 tok/s.
Projected onto a Samsung 8nm-class process (Jetson Orin Nano's process class) at 1 GHz, the conservative ASIC number is 49 tok/s, about 1.75x Jetson. NPU block area is about 2.88 mm² from 2 million combinational cells and 500,000 registers, plus 15% DFT, 70% placement utilization, and 20% clock-tree and closure overhead. Dynamic power is about 0.958 W, leakage 0.07 W, 1.335 W chip-side after SoC and clock management, and that still ignores clock and power gating the architecture already supports. Perf/watt is 36.7 vs 10.8 tok/s/W, 3.4x. Both power numbers include host plus accelerator compute and exclude memory controllers.
With Jetson-class external bandwidth, tile ingress remains the narrowest stage at about 64 GB/s, and the architectural ceiling is about 95 tok/s.
Qwen3 running on Redwood was wired back in as an inference endpoint. Repeated sampling found timing and kernel tweaks for some of its own ops at what the paper calls zero inference cost. That is the recursive-self-improvement demo.
The microarchitecture is a familiar edge NPU: tiles, dataflow, engines cut for attention and GEMM. The part worth tracking is the loop. A spec change that can be regenerated, verified, and burned onto an FPGA in 48 hours is a different planning problem than a 9-12 month freeze cycle. Teams would not need to over-generalize silicon against models that do not exist yet.
Nobody can buy this chip. It is an FPGA build plus a paper projection. What is usable today is the existence proof: AI-written RTL and UVM can stand up an accelerator that runs a 0.6B model, past the toy-core stage. If zero bugs from sim to FPGA reproduces, that result outranks the throughput table.
The 3.4x perf/watt figure is an 8nm projection against 28 tok/s at 2.59 W, not silicon.
The measurement gap is the main issue. The title and abstract say frontier and production-worthy. The evaluated model is Qwen3-0.6B. The FPGA is slower than the Jetson baseline. Llama and multi-billion-parameter models appear in the abstract; the tables do not.
All ASIC numbers are gate-equivalent area and αCV²f power, calibrated from FPGA, not 8nm silicon. The authors list physical design, tapeout, and post-silicon validation as future work. The power comparison drops memory controllers, on a workload the roofline says is memory-bound.
Two weeks with no humans below the spec assumes the platform and toolchains were already built and the spec was already written. 115 merges in a day is iteration density, not evidence that the generated architecture beat a human PPA baseline. The SIMD search is described as free to leave what humans think is optimal; the paper does not table those candidates against a hand-designed engine.
The recursive-self-improvement result is Qwen, running on the FPGA, proposing kernel and timing tweaks. That is several steps short of a model designing the next chip that then trains a stronger model, a gap the paper draws itself.