A Time-Encoded Analog Photonic Interposer for Energy-EfficientIntegration of Analog Vision Sensors and Analog Accelerators
Subhradip Chakraborty, Zihan Yin, Xuming Chen, Chengwei Zhou, Gourav Datta, Akhilesh Jaiswal
cs.AR
2026-09-03
Time-encoded photonic interposer ships analog IPC activations at implicit 6-bit, one wavelength per PE. At 10 mm GS, EDP is 2.04× vs 8-bit electrical; ResNet18 89.87% on VWW.
In-pixel computing (IPC) can finish the first convolution on the sensor plane and still leave the activations analog. Shipping those values to an analog accelerator on another chiplet usually means ADC then DAC on an electrical interposer. As distance grows, resistive loss and capacitive loading force repeated digitization, and the energy saved by analog compute is spent on the link. Silicon photonics has the bandwidth and the parasitics for long-reach chiplet traffic, but prior photonic interposers carry digital data. Microring resonators (MRRs) offer only 15–25 dB extinction, which is a poor channel for analog amplitude.
Wisconsin–Madison and Case Western build a time-encoded analog photonic interposer: voltages become timing intervals, ride a WDM link, and are reconstructed at the receiver, without an explicit high-precision ADC/DAC pipeline.
The demo has three pieces: an IPC sensor that runs the first convolution and emits analog activations; a silicon-photonic interposer for the long hop; an analog accelerator for the remaining layers (the accelerator follows prior analog DNN designs). Electronics are GF 22nm FDSOI; photonics are GF 45SPCLO. The IPC turns a Processing-in-Pixel-in-Memory cell fully analog: 3T CIS pixels Cu–Cu bonded to fixed-weight transistors, accumulated on the column. Signed convolution uses two exposure cycles; analog CDS computes (V+ − V−)/3. Activations sit in low-leakage IGZO gain cells until the analog-to-time converter (ATC) reads them.
The transmitter is a 6-bit single-slope ATC: a 1 GHz 6-bit counter drives a CDAC ramp, a strong-arm comparator flips when the ramp crosses the IPC voltage, and two voltage levels bias the MRR PN junction. Information lives in the edge time, not in optical amplitude. At the receiver the MRR sits off-resonance; a photodiode plus TIA thresholds the pulse and enables a matching ramp, which is sampled onto a PE capacitor when enable falls. No digital codeword, no SerDes. One wavelength per PE, independent of precision. A K=3 second layer uses nine wavelengths for spatial demux, with weights stationary and activations streamed. A 6-bit digital photonic link would need six wavelengths per value and would hit the platform FSR.
The ATC takes 64 cycles (64 ns), 15.6 MS/s per wavelength, about 140 MS/s across nine wavelengths. Thermal calibration is 1 pJ/value, about 15% of link energy. The interconnect is 6.6 pJ/value (7.6 pJ with calibration). Against a 10 μs IPC compute cycle, link latency can hide in the pipeline.
At L = 10 mm on 560×560 Visual Wake Words:
| metric | analog RS | analog GS | digital RS | digital GS |
| energy (μJ) | 1.16 | 1.30 | 1.32 | 1.47 |
| latency (ms) | 8.96 | 0.79 | 8.96 | 1.44 |
| EDP (nJ·s) | 10.44 | 1.04 | 11.91 | 2.13 |
| normalized EDP | 9.98 | 1 | 11.39 | 2.04 |
The 2.04× figure is global-shutter against a column-parallel 8-bit SAR electrical baseline. In rolling shutter the interconnect is pipelined with per-row compute, so the link advantage shows only for L > 30 mm. Against a precision-matched 6-bit electrical baseline the GS advantage is still 1.31× at 10 mm and 10.07× at 25 mm: longer links favor optics. The analog IPC itself reports 1.68/118.16 GOPS and 21.61/17.92 TOPS/W for RS/GS.
Combined front-end variation, including the link, is about 14.41%; deeper layers assume 0.6% accelerator noise. Accuracy:
| method | VWW R18 | VWW MBv2 | CIFAR-10 R18 | CIFAR-10 MBv2 | ModelNet40 R18 | ModelNet40 MBv2 |
| digital | 91.64 | 87.16 | 93.81 | 89.37 | 82.70 | 76.54 |
| IPC only | 91.38 | 87.69 | 93.43 | 89.21 | 82.62 | 75.20 |
| IPC + photonics | 89.87 | 86.15 | 92.92 | 88.90 | 82.29 | 74.84 |
Worst-case drop stays under 2% (1.77% / 1.01% on VWW). Silicon MRR measurements show why amplitude analog is a bad idea: at high PN bias the level spacing shrinks, which is the hardware reason to encode in time.
The target is an edge vision stack that splits an analog sensor and an analog accelerator across chiplets at centimetre reach. Time encoding decouples wavelength budget from bit precision, and a timing error becomes a small voltage offset rather than a digital bit flip. Designs that use photonics for PE-to-PE digital tensors inside an accelerator are solving a different problem; this link is for analog activations over distance. The numbers are PDK simulation plus MRR silicon, not a taped-out camera.
EDP comes from GF PDK simulation, not a full-system chip measurement. MRRs were measured on GF45SPCLO; the TX/RX chain is transient analysis plus a 1000-sample Monte Carlo. Implicit 6-bit quantization is not "unquantized analog." Rolling shutter does not win at short reach (normalized RS EDP stays 9.98 in the table). Accuracy tests set the digital baseline input to 224×224 so activations match the 560×560 analog front-end after stride, so resolution is not actually equal. The 0.6% accelerator noise is inherited from prior analog DNN work, not measured on this photonic link. FSR caps wavelength count for larger kernels. The venue is ASP-DAC, an architecture-exploration paper.