TSMC unveils BEOL oxide-semiconductor memory: 0.75V operation, sub-8ns R/W cycles
Terminator857 · reddit · 2026-11-07
At the 2025 VLSI Symposium, TSMC presented an oxide-semiconductor 1T1C memory technology aimed at integrating low-power, low-latency cache directly into advanced logic chips.
- The memory array is built into the BEOL interconnect layers of the logic die, unlike conventional separate-chip DRAM; select transistors use oxide-semiconductor channels and capacitors are fabricated with a low-temperature process
- The test chip, integrating memory and logic on a single die, operates at 0.75V, with data retention over 128ms, random read/write cycles under 8ns, and endurance above 10^14 cycles
- Positioned as a processor cache denser than SRAM with comparable power and latency
Separately, TSMC is reported to be exploring 3D DRAM production, putting it in competition with Samsung, SK Hynix and Micron.
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