Beating the compiler at signed 32-bit division: multiply-shift tricks cut latency
lemire · x · 2026-10-31
Daniel Lemire publishes a deep dive on beating the compiler at signed 32-bit division. Integer division is slow (multi-cycle latency on Zen 4/5, x86 idiv, Apple sdiv) while a multiply takes 3 cycles, so compilers rewrite division by a constant as multiply-and-shift (Granlund–Montgomery, 1994). Lemire shows that with signed 32-bit integers on 64-bit systems you can often do better than GCC/clang: his fastmod benchmarks hit 3.2 ns vs 4.0 ns for the division instruction on Intel (GCC 14), 2.9 ns vs 4.0 ns with clang 21, and 2.0 ns on Apple M4, with latency charts for divisors like 7, 60, 365 and 1000.
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