Chip scaling's three eras: CMOS shrinks gave only efficiency after 2015, says blelbach
blelbach · x · 2026-09-17
blelbach lays out three eras of how Moore's Law surfaced to users: 1970-2005 the "Free Lunch" era of scaling clock speeds; 2005-2015 the "No More Free Lunch" era of scaling core counts; and 2015-202? "Software Hell," where gains came from specialization — GPUs, low precision, tensor cores. He notes CMOS transistor shrinks have been about power efficiency rather than raw speed since 2015, and that route is nearly exhausted. Recent packaging techniques (stacking, substrates) have kept "chip" scaling alive on the datacenter side, where room remains.
Related event: Veteran: CMOS Scaling Is Tapped Out, Sparsity Is AI's Next 10x(4 posts)→
More from Infra
- Marvell-Lumentum deal signals what it takes to compete with Broadcom — BenBajarin · 2026-11-02
- Sam Altman: AI query energy cost fell 1,000x-100,000x in 3-4 years — rohanpaul_ai · 2026-11-02
- Marvell and Lumentum to merge, targeting $550B AI connectivity market — BenBajarin · 2026-11-02
- Samsung chairman visits Yokohama advanced packaging lab, pledging ¥40B investment over five years — pstAsiatech · 2026-11-02
- Sam Altman meets Samsung executives in Korea to deepen memory chip and AI infrastructure cooperation — pstAsiatech · 2026-11-02
- Simulating 200,000 months: can your home AI rig pay rent at 2026 GPU prices? — LeviTurk · 2026-11-02