Chip scaling's three eras: CMOS shrinks gave only efficiency after 2015, says blelbach
blelbach · x · 2026-09-17
blelbach lays out three eras of how Moore's Law surfaced to users: 1970-2005 the "Free Lunch" era of scaling clock speeds; 2005-2015 the "No More Free Lunch" era of scaling core counts; and 2015-202? "Software Hell," where gains came from specialization — GPUs, low precision, tensor cores. He notes CMOS transistor shrinks have been about power efficiency rather than raw speed since 2015, and that route is nearly exhausted. Recent packaging techniques (stacking, substrates) have kept "chip" scaling alive on the datacenter side, where room remains.
Related event: Veteran: CMOS Scaling Is Tapped Out, Sparsity Is AI's Next 10x(4 posts)→
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