Paper envisions 3D EIC-PIC stacks with layered RAM and photonics on XPU; commenters doubt the thermals
jwt0625 · x · 2026-11-11
The Yoo2026 paper "Hybrid Bonding and Packaging Technologies for 3D EIC-PIC Integration and Future 3D EPICs" lays out a futuristic 3DHI-EPIC architecture: stacking layers of DRAM, MRAM, silicon photonic PICs and III-V photonics on top of XPU/CMOS ASICs via DBI hybrid bonding, with TSV/TSOV vertical interconnects, an active optical interposer and co-packaged optics.
Commenter jwt0625 poked fun at EE folks plotting "10.6 dB per year" as an AI-progress curve, and quipped that this pile of RAM layers plus EIC/PIC layers might only avoid melting "if we swap the silicon oxide with diamond" — flagging thermals as the biggest reality check for the vision.
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