Grand challenge: design a 3W, 64-bit RISC-V compute subsystem for real-time mobile XR on 3nm
satnam6502 · x · 2026-11-09
- A tweet shares a conference slide (reportedly from the IET REACH 2026 computer architecture conference in London) posing a "Grand Challenge": design a low-power, 64-bit RISC-V-based compute subsystem for an XRBench-class real-time mobile XR workload, within a 3W thermal envelope on a 3nm-class low-power process.
- The slide stresses the format: "a specification goes in, an evaluated design comes out, and a named engineer signs off. Not type-a-sentence, get-a-chip" — i.e., real, verifiable engineering deliverables rather than AI hype around one-shot chip generation.
Related event: AI Designs 64-bit RISC-V Chip in One Prompt at IET Conference(2 posts)→
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