AI-generated systolic arrays verified with mutation testing to keep correctness theorems honest
satnam6502 · x · 2026-11-07
satnam6502 shares details of a hardware-generation pipeline: the systolic array matrix multipliers and their tests were AI-generated.
The verification step is the interesting part: alongside generating the implementation and a correctness theorem, they used mutation testing — deliberately breaking the implementation to confirm the correctness theorem could no longer be proven, ensuring the theorem genuinely connects the specification to the implementation rather than being vacuously true. A practical anti-cheat technique for AI-generated formally verified hardware.
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