Aristotle formally verifies FP16 systolic matrix multipliers up to 64x64 in Lean 4
satnam6502 · x · 2026-11-07
Researcher satnam6502 shared Aristotle formal verification reports for systolic array matrix multipliers.
- Covers sizes 4x4, 8x8, 16x16, 32x32 and 64x64 for FP16 values.
- Reports include properties verified in Lean 4, the SystemVerilog code, and verification summaries.
- Verification directly compares the hardware against a high-level functional specification of a pipelined systolic multiplier — an approach the author notes is unusual.
- An accompanying diagram visualizes the cycle-by-cycle dataflow and accumulation across processing elements in a 4x4 array.
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