ETH Zurich releases full open-source VLSI course: 12 lectures plus OpenROAD-based exercises
Obijuan_cube · x · 2026-11-06
ETH Zurich's Integrated Systems Laboratory (Luca Benini and Frank K. Gürkaynak) has opened up its complete VLSI design course under Creative Commons BY.
Key points:
- Curriculum: 12 lectures covering SystemVerilog, synthesis, IC manufacturing, floorplanning, timing, parasitics, back-end design, power analysis, DRC/LVS and ATPG testing, with 2026-version PDF slides for each.
- Fully open-source EDA flow: exercises use Verilator, GTKWave, Yosys, OpenROAD and KLayout together with IHP's open PDK; only a few steps (Siemens Calibre, Synopsys tools) remain commercial.
- Croc SoC: hands-on work centers on Croc, a simplified open-source SoC from the PULP platform with an Ibex core, OBI crossbar, iDMA and SRAM banks, where students extend their own designs.
A rare, systematic free resource for anyone wanting to learn the full RTL-to-GDS chip design flow.
More from Companies & People
- Mystery OpenAI gift card with giant smiling face shows up at AI researcher's doorstep — Yuchenj_UW · 2026-11-06
- Analyst: "Anthropic is after our data" is becoming the go-to grifter pitch — teortaxesTex · 2026-11-06
- Physical AI meetup in India: 4 robotics founders on real factory deployments and eval loops — carrycooldude · 2026-11-06
- Boom founder: only ~5 of 165 staff work on supersonic jet as energy comes first — dunkhippo33 · 2026-11-06
- xAI inference and kernel engineer departs, citing SGLang, attention kernels and C++ inference stack rewrite — HanchungLee · 2026-11-06
- Design teams aren't being cut for lack of work—the bar has fundamentally risen in the AI era — LadyAshBorg · 2026-11-06