Aristotle system machine-checks Ibex RISC-V core MUL operation formally
satnam6502 · x · 2026-10-31
Demonstrated at a University of Glasgow seminar on formal verification, the Aristotle system formally proved the MUL operation of the Ibex RISC-V core against a SAIL-generated SystemVerilog assertion. The screenshot shows the agent completed the proof in 9m51s over 66 steps: assertmul holds in every cycle of every execution, with no counterexample and no defects found in the Ibex RTL, the SAIL-generated module, or the harness — a complete, machine-checked proof.
Related event: Harmonic Engineer Showcases Aristotle Formal Verification Wins(3 posts)→
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