Teralynx T100 sparks back-of-envelope math on the path to one-petabit AI switches with 640 MMC connectors
jwt0625 · x · 2026-09-09
Discussing Marvell's Teralynx T100 AI data center switch (16×4 OSFP cages, 512×200G lanes), the author sketches what a one-petabit switch would take: doubling lane rates implies 5x the OSFPs, or 40 XPOs, or 640 MMC connectors with 5,120 active fibers plus CPO.
He notes Nvidia's planned SN6800 already uses 512 MMCs (with 4 ASICs), showing the path isn't sci-fi. With 8+8 DWDM lighting 8 fibers per MMC, you'd approach one MMC per scale-up ASIC.
Related event: Marvell Teralynx T100 and Petabit Switches Aim to Break the Network Wall(2 posts)→
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