40-nm Memristor Chip Turns Conductance Drift Into a Feature, Beats A100 by 50-480x

maier_ak · x · 2026-09-01

Andreas Maier breaks down a compute-in-memory paper: a 17-author team built a 40-nm PCM (phase-change memory) ASIC that embeds the entire neural-dynamical-system (NDS) integration loop inside the memory elements themselves.

Key idea: PCM devices suffer notorious conductance drift, normally a defect. The authors harness that drift as a physical adaptive-stepsize controller, eliminating the step-size search that dominates NDS latency in digital implementations (the von Neumann bottleneck hits NDS hard since the algorithm shuffles data thousands of times per step).

Results:

Single-iteration integration latency of 2.12 ms while meeting a 10⁻⁷ error bound
3.8–36x faster than the best published NDS accelerators at 12–25x less power
16-level cells store neural weights and Δt values
The 0.28 mm² chip completes a cortex-surface reconstruction benchmark in 0.426 s, a 50–480x speedup over an NVIDIA A100
Could enable sub-10 ms cortical-mesh updates for real-time neurosurgical guidance

NDS couples a neural network with a continuous-time ODE solver, producing topology-preserving (genus-0) smooth deformations critical for high-fidelity geometry tasks like reconstructing the folded human cortex.

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40-nm Memristor Chip Turns Conductance Drift Into a Feature, Beats A100 by 50-480x

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