40nm Neural-Dynamics Chip Uses Conductance Drift for 2.12ms Iteration Latency
maier_ak · x · 2026-09-01
Researchers have developed a 40nm phase-change memory (PCM) ASIC that embeds the entire neural-dynamical-system loop in hardware. By using controlled conductance drift as a physical adaptive-stepsize mechanism, the chip achieves a single-iteration integration latency of 2.12 ms while meeting a $10^{-7}$ error bound.
Related event: 40nm PCM ASIC embeds neurodynamics in hardware, 50-480x faster than A100(2 posts)→
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