NVIDIA H100 Concurrency Response of Plain Global Loads Analyzed
ssh4net · x · 2026-08-19
This paper analyzes the concurrency response of Plain Global Loads on NVIDIA H100 SXM5 GPUs. Utilizing Little's Law and clean-room microbenchmarks, the study characterizes how CUDA fills the throughput budget via plain loads and asynchronous copies. A key finding reveals that attained LDG bandwidth peaks at a small per-thread load (K≈2) and then declines by approximately 35% as K increases to 8. This performance degradation persists across various control configurations, highlighting specific behavioral traits of the Hopper architecture.
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