If AI ends compilers, EDA flow dies and formal verification becomes key
satnam6502 · x · 2026-08-17
Author argues that if AI renders compilers obsolete, the SystemVerilog EDA flow will die, replaced by direct generation from formal specs to gates. This shift necessitates formal verification of AI-generated silicon, including analog VLSI behavior. Lean 4 + Mathlib is suggested as a starting point.
More from AGI Musings
- Economics paper submissions nearly double post-ChatGPT, referee shortage suggests submission fees must rise to $410 — JMateosGarcia · 2026-08-17
- Humanoid robot future: tens of thousands to Mars, hundreds of millions to homes, billions to workplaces — davidpattersonx · 2026-08-17
- Always Be Commoditizing: The Norm in Tech Competition — docmilanfar · 2026-08-17
- Workers' income drops only 5% after occupation shrinks 25% — paulnovosad · 2026-08-17
- AI lacks survival instincts and emotions; fear stems from human ignorance — davidpattersonx · 2026-08-17
- Economist slams AI-written papers: Formulas are all wrong — joshgans · 2026-08-17