NVIDIA and ETH Zürich cut small-message AllReduce latency by deleting barriers
thoefler · x · 2026-07-22
NVIDIA and ETH Zürich cut small-message AllReduce latency by deleting a global barrier
The post points to The Barrier Tax, an arXiv paper from NVIDIA and ETH Zürich about long-context decode. The key observation is that once KV cache growth shrinks batch sizes, collectives stop being bandwidth-bound and become synchronization-bound.
What the paper measures
- In a 5 µs AllReduce across 4 GPUs, global synchronization can account for about 40% of latency.
- On GB200, a single global memory barrier costs over 1 µs; many AllReduce kernels need two.
What they changed
- LL: pack an 8 B flag into a 16 B atomic store.
- Sentinel: prefill a slot with −NaN and poll until it changes.
- Double buffer: run one iteration ahead.
- LL128 atomic: use cache-line atomics and reduce in place.
Reported gains
- 2.37 µs latency for the barrier-free kernel vs 11.0 µs for NCCL ring in the figure.
- About 4.6× faster than the ring baseline in that small-message case.
- Estimated 7–13% inter-token latency reduction at 4 GPUs, 9–11% at 8 GPUs.
- Roughly 0.9% cost reduction per microsecond removed.
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