A silicon photonic reservoir chip compensates fiber distortion in real time at 28 Gbps
bravo_abad · x · 2026-07-21
A silicon photonic reservoir chip equalizes fiber distortion at line rate
Researchers built a silicon photonic chip that combines a fixed reservoir computing core and a programmable optical readout on the same die, so the whole inference path stays in the optical domain.
- The reservoir uses 8 passive nodes built from multimode interferometers and waveguides.
- The readout is another 8 Mach–Zehnder interferometers whose heaters act as complex-valued weights.
- Weights are tuned with CMA-ES using the hardware in the loop, letting device quirks and thermal crosstalk be absorbed during training.
The chip was tested on a real optical-fiber task: compensating chromatic dispersion and Kerr nonlinearity on a 28-Gbps signal over fiber links up to 50 km.
- Lowest reported BER: 4 × 10^-7
- That is below the FEC threshold and at least 100× better than a matched digital feed-forward equalizer.
- Inference runs at full line rate, with only about 243 ps of chip latency.
The broader takeaway is that as inference cost and latency matter more, physics-as-compute plus hardware-in-the-loop training could become useful beyond photonics, including for low-power edge sensing and real-time control.
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