Huawei Ascend 960: From Rumor to Launch

Episode 1 · Huawei's Ascend 960DT rumored to offer 288GB memory in 2027 (2026-09-17, 3 posts)

Leaked claims say Huawei's Ascend 960DT will launch in Q1 2027 with 288GB of memory, a major spec jump for domestic AI chips, though observers question where the memory supply will come from.

• Huawei Ascend 960DT reportedly due Q1 2027, fp4 support starting from 960PR — zephyr_z9 · 2026-09-17
• Huawei Ascend 960DT rumored with 288GB memory in Q1 2027, supply questioned — zephyr_z9 · 2026-09-17
• Huawei's Ascend 960DT to Offer 288GB in Q1 2027, Likely LPDDR-Based — bookwormengr · 2026-09-17

Episode 2 · Huawei Unveils Ascend 960 and UnifiedBus, Targeting Million-Chip AI Clusters (2026-09-17, 6 posts)

At HUAWEI CONNECT 2026, Huawei rolled out a next-generation AI compute stack aimed squarely at Nvidia: the Ascend 960 chip family, the Atlas 960E SuperPoD, the UnifiedBus (Lingqu) interconnect, and OceanStor M900 memory storage, all targeting a single AI supercluster of up to one million processors. 960DT mass production was pulled forward by three quarters and is widely read as a bellwether for China's AI compute and chip supply chain.

Confirmed

• Accelerated roadmap: Per @markk and @GlennLuk, Ascend 960DT mass production moved from Q4 2027 to Q1 2027; both 960DT and 960PR are slated for 2027, with doubled compute of 2 PFLOPS (FP8)/4 PFLOPS (FP4), up to 288GB HBM and 9.6TB/s bandwidth.
• Interconnect: UnifiedBus links CPUs, NPUs and DPUs and is designed to connect up to one million processors into a single AI supercluster.
• SuperPoD and Peerium: Rotating Chairman David Wang unveiled the Atlas 960E SuperPoD, the industry's first NPO-based SuperPoD supporting up to one million NPUs — "a million cards as one machine" — alongside the Peerium architecture.
• Efficiency: Per @智东西, MFU of 100K-GPU clusters rises from under 20% with traditional interconnects to 35% with UnifiedBus.

Why it matters

• The roadmap is widely seen as a bellwether for China's AI compute and chip supply chain, benchmarked directly against Nvidia.
• @GlennLuk suggests the 960 may be the first AI accelerator after the Kirin 950 Pro to use LogicFolding architecture; since accelerators impose far higher die-size, packaging and power demands than phone SoCs, this is offered as one deep reason for the pull-in (analytical speculation).
• The large MFU gain from UnifiedBus significantly improves real-world utilization at scale, a key step toward making million-chip clusters engineering-feasible.

• Huawei Unveils Ascend 960 Chips and SuperPoD Stack Aiming at Million-Card Clusters — 智东西 · 2026-09-17
• Huawei pulls Ascend 960DT forward to Q1 2027 with 2x compute, but smaller SuperPoD — GlennLuk · 2026-09-17
• Huawei unveils Ascend 960 chips for 2027 and UnifiedBus linking one million processors — mark_k · 2026-09-17
• Huawei's Ascend 960 to debut LogicFolding architecture amid memory reallocation clues — GlennLuk · 2026-09-17
• Huawei unveils Peerium architecture and Atlas 960E SuperPoD scaling to 1M NPUs — pstAsiatech · 2026-09-18
• Huawei's UnifiedBus lifts 100k-card MFU from 20% to 35%, unveils Ascend 960 supernode — 智东西 · 2026-09-19

Episode 3 · Huawei Unveils Ascend 960 Supernode: 4,096 Cards, 8 EFLOPS (2026-09-20, 5 posts)

At Huawei Connect 2026 on September 17, rotating chairman Wang Tao unveiled the Ascend 960 supernode, scaling to 4,096 cards with 8 EFLOPS and slated for Q3 2027 delivery. It is Huawei's first supernode using near-package optics (NPO), and its training card Ascend 960DT is Huawei's first known accelerator with HBM. The launch schedule has moved up significantly versus the original plan.

Confirmed

• Huawei (Wang Tao) announced the Ascend 960 supernode at HC2026: 4,096 cards, 8 EFLOPS, Q3 2027 delivery (m1)
• The supernode uses 5,500 self-developed NPO engines to replace roughly 48,000 800G optical modules, with volume production said to be imminent (m2)
• Ascend 960DT (training) has 288GB HBM and 4 PFLOPS FP4, launching Q1 2027, three quarters early; Ascend 960R (inference) arrives Q3 2027, three months early (m3, m4)
• Per Zhidx's analysis, Huawei's simulations show the 4,000-card supernode reaching 2.75x the MFU of traditional clusters; the context is that inter-card communication in 100k-card clusters can consume over 40% of training time with MFU often below 30%, and the supernode's unified memory addressing organizes thousands of cards into one logical computer (m5)

Unconfirmed

• @pstAsiatech notes the 5,500 NPO engine substitution is currently Huawei's claim only, with no shipments or third-party verification (m2)
• All compute and MFU figures come from Huawei's own statements or simulations, with no independent testing yet

Why it matters

• With single-chip compute still behind Nvidia, Huawei is betting on interconnect and cluster architecture to compete at the system level (m3)
• If large-scale NPO substitution of pluggable optics materializes, it could sharply cut cluster interconnect complexity and power draw—a key signal for China's AI infrastructure roadmap (m2, m5)
• The schedule pulled forward by up to three quarters signals Huawei's intent to accelerate iteration under sanctions pressure (m3, m4)

• Huawei's Ascend 960DT is its first HBM accelerator: 288GB, 9.6TB/s, 4 PFLOPS FP4 — pstAsiatech · 2026-09-20
• Huawei unveils Ascend 960 supernode: 4,096 cards, 8 EFLOPS FP8, NPO optics, Q3 2027 — teortaxesTex · 2026-09-21
• Huawei pulls Ascend 960 AI chips forward by up to 9 months to challenge Nvidia — MirelaXhota · 2026-09-21
• Huawei says Ascend 960 supernode will use 5,500 NPO engines to replace 48,000 800G optical modules — pstAsiatech · 2026-09-21
• Inside Huawei's Ascend 960 Supernode: 4,096 Cards, Unified Memory, 2.75x MFU — 智东西 · 2026-09-21