2026-08-22
Nature Electronics review maps CPO energy from ~10–20 pJ/bit in 2D to <100 fJ/bit monolithic; compute scales ~3×/2yr, interconnect bandwidth 1.4×.
HBM pushed the on-package memory wall back. The new wall sits outside the package. Accelerator counts and HBM stacks keep climbing, and the copper that moves data between chips, boards, and racks is not keeping up with compute.
This is a Nature Electronics review, not a new device paper. Groups at the University of Virginia, MIT, UIUC, NTU, Yonsei University, and SK hynix put optical compute interconnects (OCIs) and co-packaged optics (CPO) on one map, and ask how much longer electrical links can carry AI clusters.
Figure 1a overlays four curves. Hardware compute scales at about 3.0× every two years, DRAM bandwidth at 1.6×, interconnect bandwidth at 1.4×. Training compute for AI models runs at about 8.8× every two years. Resistive loss, capacitive loading, and frequency-dependent distortion on copper jointly squeeze bandwidth, latency, and energy as reach and rate go up.
The review splits system performance into three domains: electrical subsystems, electro-optical and opto-electronic conversion, and the optical transmission network. Bandwidth, energy, and latency all come out of those three blocks.
The optical link skeleton is fixed. A wide parallel bus on the compute die is serialized by SerDes, converted onto an optical carrier, wavelength-multiplexed, sent through fibre or waveguide, then converted back and deserialized. Two modulation formats dominate: NRZ puts one bit on one level; PAM-4 packs two bits into four amplitudes, doubling spectral efficiency and shrinking noise margin.
On the modulator side, a Mach-Zehnder interferometer writes electrical data onto optical intensity via path-length difference; the continuous-wave laser is typically off-chip. Short-reach links can use VCSELs that emit from the surface, with a photodiode plus transimpedance amplifier on the receive side. On-chip routing uses wavelength-selective microring resonators for filtering and multiplexing. Fibre attach comes in two flavours: grating couplers for vertical I/O, and edge couplers for in-plane alignment at lower insertion loss.
The energy ladder is set by how close the optical engine sits to the compute die. Figure 3 walks that distance down. In pluggable optics, the SoC and photonic engine sit far apart on a PCB copper trace. On-board optics parks the transceiver next to the SoC and buries a waveguide in the board. 2.5D CPO puts both dies on one interposer. 3D stacks the transceiver vertically onto the SoC.
Figure 3 annotates representative performance at each integration tier. These are survey numbers drawn from published devices and the SEM panels, not a new chip measured for this paper.
| Integration | Energy | Bandwidth |
| 2D wire bonding | 10–20 pJ/bit | hundreds of Gbps per package |
| 2.5D micro-bump interposer | 2–5 pJ/bit | 1–2 Tbps/cm² |
| 3D TSV | 0.5–2 pJ/bit | >5 Tbps/cm² |
| 3D hybrid bonding | 0.1–0.5 pJ/bit | 10–50 Tbps/cm² |
| Monolithic electro-photonic | <100 fJ/bit | >50–100 Tbps/cm² |
Energy per bit drops by about two orders of magnitude from 2D to monolithic. Radar plots spread maturity, cost, bandwidth, energy, thermal management, fabrication access, and footprint. 2D is the most mature and the easiest to build, and the weakest on bandwidth and energy. Monolithic wins bandwidth and energy, and loses on fabrication access and heat. 3D hybrid bonding sits in the middle; thermal load and cost already bite.
Figure 1b uses bandwidth density divided by energy as a figure of merit, split by in-package, on-board, and off-board reach. The electrical projection is marked as a 1 Tbps mm⁻¹ at 1 pJ/bit benchmark, and it falls as distance grows. The optical projection is flatter, which is the regime CPO is aiming at. HBM and UCIe Advanced still sit on the in-package electrical high ground; NVLink C2C has moved on-board; PCIe Gen5 and pluggable Ethernet SR4 sit off-board.
The farther picture is a photonic interposer: a compute pool and a memory pool share one waveguide-embedded substrate, with optical TSVs for vertical light routing, and even micro-LED arrays, microlens arrays, and photodetector arrays for massively parallel links that skip SerDes.
For people who run training and inference clusters, this review turns "move the optics closer" into a checkable energy ladder rather than a slogan. HBM attacked the in-package memory wall. CPO is aimed at the off-package data-movement wall. A memory vendor sits in the corresponding-author list, and the direction is explicit: optical links will eventually reach the memory interface so several accelerators can share one large memory pool.
Little of this is a purchase order today. 2D and 2.5D are already being tried in volume on switch ASICs and early optical engines. 3D hybrid bonding and monolithic integration still sit between lab and pilot line. This is a roadmap review: incremental, systemic, with no new head-to-head experiment.
The full article runs about 15 pages. Nature's paywall blocked the body. This write-up uses the public abstract plus the four figures and their captions. Thermal management, manufacturability, and standardization are named as the production gates; the quantitative case and any standards timeline sit in the unread text.
The Figure 3 numbers are labelled representative. The SEM panels are reproduced or adapted from cited papers, not a controlled comparison on one process node. How much of the two-order energy drop comes from package distance versus modulator type and laser efficiency cannot be split from the figure alone.
One corresponding author is an SK hynix employee; the competing-interest note says so. Hooking a photonic interposer to a memory pool lines up with that firm's HBM story. Treat the technical roadmap and the product roadmap as separate documents. The radar charts are qualitative; no scoring rule is given.