Agent-Orchestration in Autonomous Chip Design
Linyang Li
cs.AI
2026-08-14
Nova Silicon argues chip-design superintelligence should be an AI organization, not a rule pile, but offers no experiments for the speed claim.
Chip design is a long, fragmented flow whose rules have accumulated for decades. Coding agents shifted the speed metric from a fraction of a human to a fraction of the model. People now want that autonomy in EDA. This Nova Silicon position paper asks what kind of AI a field this intricate actually needs. The answer is blunt: model chip-design superintelligence as a large AI organization, not as a chat window bolted onto today's tools.
The argument has three parts and no implementation.
First, one experimental trial is an action space. Analog transistor sizing is the running example: widths and lengths of five MOS devices give a 10-dimensional continuous space; objectives include gain, bandwidth, phase margin, and power; constraints come from the PDK and saturation. A black-box optimizer feeds a (W, L) vector into a simulator and reads metrics back, with no analytic gradient. Two points matter. Many points inside the hyperrectangle are physically illegal because matching rules collapse the feasible set onto a lower-dimensional manifold. The curse of dimensionality is why grid search dies and why Bayesian optimization looks attractive relative to brute force. In practice, shrinking the action space with design priors often beats swapping the optimizer. Topology synthesis, place-and-route, and architecture search still lack a clean action-space definition.
Second, language-model reasoning is contrasted with classical black-box search. BO sees floats. It does not know transconductance gm or gm/ID methodology, and a new topology forces a cold start. Human sizing sets a target gm, picks bias current, then backs out W/L. An LLM, the paper argues, carries device physics and design method in pretraining, can avoid triode operation and enforce matching before any sim, and can emit a transferable rationale such as raising input-device W to raise gm.
Third, a complex-circuit agent should not be a flowchart with enumerable branches. Autonomous agents plan, call tools on demand, and collaborate, which a static graph cannot bound. The proposed host is an object-oriented organization: encapsulation, messages, private state, extensible behavior. Contemporary EDA is split into a physics simulator and handwritten heuristics. Simulation is a physics, model, measure, calibrate, validate loop. Heuristics compress decades of experience into rules that cut an intractable combinatorial space down to something solvable. Conventional ML fits the sparse traces those rules already produced, so it cannot cover long-tail joints where every factor was seen alone and the combination never was. The proposed path uses LLM symbolic reasoning in two stages: first copy how engineers think on tasks that still need hands; then learn from cases and simulation feedback to thin out the legacy rule pile. That is a different claim from attaching a model to an existing flow.
There are no experiments. No circuits, no benchmarks, no baselines. The closing sentence says end-to-end autonomous AI is inevitable and tens to hundreds of times faster than human-in-the-loop design. The paper never defines that speedup, nor measures it. The only numbers in the body are pedagogical: Lmin of 0.028 μm on a 28 nm process, and a 10-dimensional space for five transistors. Mirhoseini et al. 2021 is cited as a reminder that learned placement policies must sit inside the EDA flow, not as a result of this work.
The paper lifts "chip-design agent" from a plugin question to an organizational one, and it states three problems practitioners actually hit: action-space pruning, physical priors, and combinatorial long tails. For someone building an analog sizing agent or an EDA copilot, this is a problem map: get the action space right before arguing about the model. Recent sizing agents with numbers, including AnaFlow, ADO-LLM, and Ledro, already run LLM priors against a simulation loop; this piece isolates the philosophy underneath that line of work.
Treat the argument and the company story as separate. The author is at Nova Silicon, and the claim batch also carries discussion about SenseTime investment. A position paper can point; it cannot substitute for a bake-off.
No system, no ablation, no numeric comparison with BO, RL, or existing LLM sizing papers. "Object-oriented AI organization" stays a slogan: no org chart, no role protocol, no failure recovery. The physics-simulation section is correct, and it never says how LLM reasoning gets through the calibration loop instead of talking past measurement. The speedup is an untested assertion. For tasks whose action space is still undefined, the paper also does not give an operational modeling recipe.