Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena
Haocong Luo, Longda Zhou, Ataberk Olgun, İsmail Emir Yüksel, Nisa Bostanci, Zhigang Ji, Xing Wu, Onur Mutlu
cs.AR, cs.CR
2026-07-30
Bridges RowHammer real-chip data with TCAD device modeling: bitflip direction is set by which neighboring wordline holds the charge trap, and 1-to-0 vs 0-to-1 flips barely overlap (mean Jaccard 1.5%–6.8%).
DRAM has a stubborn flaw: hammer a row enough times and the data in neighboring rows you never touched can flip on its own, 1 turning to 0 or 0 to 1. That is RowHammer, and its variant RowPress holds the attacking row active for a long time instead of toggling it. Small consequence: silent data corruption. Large consequence: a real privilege-escalation primitive that breaks memory isolation.
Two camps study it, and they disagree. Experimentalists measure real chips, counting bitflips and the minimum activations needed to flip the first bit (ACmin). Device-level modelers run TCAD simulations from transistor physics. The models fail to explain everything the chips show: by theory, double-sided RowHammer should amplify only 1-to-0 flips and suppress 0-to-1, yet real chips produce both. This paper reconciles the two and lays a foundation for the next round of understanding, measurement, and defense. The team is from ETH Zurich (Onur Mutlu's group), East China Normal University, and Shanghai Jiao Tong University.
Three legs. First, real-chip characterization on commodity DDR4 from multiple vendors, run through the group's own FPGA rig, DRAM Bender; RowPress is measured at 80°C, where it bites harder. Second, TCAD simulation: a saddle-fin recessed-channel structure in Sentaurus, calibrated to 1z-nm process geometry, voltages, and capacitances. Third, wafer-level electrical measurements on fabricated sub-20nm test structures.
A key move is reverse-engineering which neighboring aggressor wordline is which. Each victim row sits between two aggressor wordlines: the nearer one is the NWL (neighbor wordline) and the farther one is the PWL (passing wordline). They infer each line's identity from bitflip direction and cross-check against measurement; nearly every module comes back 100% consistent.
The whole analysis is anchored on three metrics that should each trace to a first-order physical mechanism: bitflip direction (1-to-0 vs 0-to-1), bitflip count, and ACmin.
They first list three places where the model says one thing and the chips say another, then close each. The headline: bitflip direction is decided by which side the charge trap sits on. A trap near the NWL amplifies 1-to-0 and suppresses 0-to-1; near the PWL, the reverse.
The evidence is unusually direct. Under double-sided hammering, the 1-to-0 and 0-to-1 flips barely share physical cells. Mean Jaccard overlap across modules is only 1.49%–6.77%; module S4 hits 6.65% and 6.77%, and module M0 just 2.57% (50°C) and 2.77% (80°C). The cells that flip 1-to-0 and the cells that flip 0-to-1 are largely different grids, which is exactly what "trap location sets direction" predicts.
On raw counts, double-sided hammering cuts the activations needed to trigger a flip substantially: 75.5% lower on the NWL side and 74.7% on the PWL side, versus single-sided. The 0-to-1 flip needs fewer activations than 1-to-0 because its electron-migration path is shorter and more efficient. Push the hammer count high enough and 1-to-0 overtakes 0-to-1, because today's DRAM processes tend to seed more traps near the NWL.
| Observation | Device-level factor | Mechanism |
| Double-sided hammering yields both 1-to-0 and 0-to-1 | Charge-trap location | NWL-side traps drive 1-to-0, PWL-side drive 0-to-1 |
| 0-to-1 has smaller ACmin than 1-to-0 | Electron-migration path length | Shorter path, higher efficiency, faster flip |
| At high count, 1-to-0 outnumbers 0-to-1 | Process-induced asymmetry | NWL-adjacent region is more vulnerable |
For RowPress, the model had predicted 0-to-1 flips from the NWL side, but none show up under normal operating conditions: the leakage is too weak to beat the cell's intrinsic retention leakage. On the PWL side, the RowPress 1-to-0 flip is highly sensitive to the bulk hole-trap density (DHT,bulk), which is also the dial that decides whether simulation matches silicon. A counterintuitive one: for PWL RowPress, ACmin for both 1-to-0 and 0-to-1 decreases as the aggressor on-time (tAggON) grows, rather than bottoming out the way competing-mechanism intuition expects.
Every RowHammer defense is ultimately a fight over ACmin: you assume what an attacker can reach, then set refresh rates or row-migration triggers accordingly. The practical warning here is that today's "statistical bitflip" system-level models are too crude, because they treat 1-to-0 and 0-to-1 as interchangeable random events when the two have different, sometimes competing, physical drivers.
The sharper methodological point: do not estimate ACmin from the bit-error rate (BER) at a high hammer count. BER is easy to measure, but it is not a proxy for ACmin, because the two flip mechanisms evolve differently as the count climbs. If you design DRAM robustness tests or set thresholds, that distinction changes how you work.
For practitioners, this is groundwork rather than a product. It does not hand over a new system-level model ready to drop into a simulator; the authors say explicitly that is future work. What it does is explain why prior models misfired, and it points at what comes next: combined RowHammer-and-RowPress access patterns, temporal drift of the flip threshold, and emerging disturbances like ColumnDisturb.
The authors concede that the systematic excess of 1-to-0 over 0-to-1 at high hammer counts has only a qualitative explanation (the process leaves more traps near the NWL); pinning down the exact manufacturing root cause quantitatively is out of scope.
The simulations use a single-trap configuration for sensitivity analysis (later extended with interface-trap density), while real chips hold many traps; whether that simplification misses coupling effects is not fully ruled out. The TCAD structure is pinned to one 1z-nm saddle-fin process, and generalization to other nodes or architectures, such as more aggressive buried-wordline or 3D DRAM, is unverified.
Coverage is limited to RowHammer and RowPress; their combinations, threshold drift, and ColumnDisturb are explicitly flagged as future work. And it is understanding and guidance, not a deployable artifact. To harden a system with this, you have to wait for the system-level model it calls for.