Zen 6 details: four 256-bit vector loads per core per cycle, faster VNNI throughput

lemire · x · 2026-11-13

Chips and Cheese published an interview with AMD chief architect Mike Clark on Zen 6; lemire distilled the key changes vs. Zen 5:

Vector loads: each core sustains four 256-bit vector loads per cycle — AMD already led here, and Zen 6 pushes further.
Integer multipliers cut from three to two: the third added little; sustained 3 multiplications per cycle is rare, and AMD backtracked.
Branch mispredict recovery is faster with no accuracy loss.
VNNI (AI dot-product) instructions now sustain nearly four 512-bit instructions per cycle — a lot of compute.

The interview also covers Zen 6 vs. Zen 6c differences and the reasoning behind the changes.

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