Dev runs SmolLM-135M inference entirely in SystemVerilog via Verilator

cneuralnetwork · x · 2026-11-08

A developer implemented the entire SmolLM-135M inference path — tokenizer, 30 decoder layers, KV cache, vocab projection, and text decoder — in a single SystemVerilog file, executed in the Verilator simulator with outputs matching a PyTorch reference.

Key details:

smollm.sv reads lookup tables via $readmemh, parses the 538MB model.safetensors checkpoint directly (576-dim hidden state, 9 query heads), decodes F32 weights into Verilog reals, and runs the transformer
An optional Node.js Prompt Studio dashboard just launches the binary and relays progress; Node never tokenizes or picks tokens
The author is explicit about the boundary: this is behavioral SystemVerilog using reals, strings, and file I/O — not synthesizable FPGA/ASIC logic. The experiment asks whether the full model path can be expressed in SystemVerilog, not whether it's a deployable chip design

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Dev runs SmolLM-135M inference entirely in SystemVerilog via Verilator

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