AI-generated systolic array multipliers verified with mutation tests and theorem proving
satnam6502 · x · 2026-11-07
- Satnam Singh reveals his systolic array matrix multipliers were AI-generated, along with their tests; the accompanying figure shows the mathematical definition of outputs c{i,j} capturing same/time-pipelined behavior for the N=4 case.
- The process included mutation testing: deliberately breaking the implementation to confirm the correctness theorem no longer proves, ensuring the theorem genuinely connects specification to implementation.
- The SystemVerilog specification is a direct transcription of that definition, showcasing a full AI-generated-hardware-plus-formal-verification workflow.
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