RISC-V Day Tokyo 2026 unveils agenda with Google TPU v3 on display and 2nm AI accelerator talks
DavidBennett__ · x · 2026-11-04
RISC-V Association Japan has published the updated program for RISC-V Day Tokyo 2026 Autumn, held November 11 at the University of Tokyo's Hongo Campus.
Highlights include:
- Tenstorrent's Thaddeus Fortenberry on Physical AI, plus talks on Open Chiplet Atlas interoperability and semiconductor design talent development;
- AIST presenting 2nm-generation edge AI accelerator development;
- A physical Google TPU v3 on display, alongside the Chip Museum and RISC-V research demos;
- Morning parallel tutorials on digital logic design and analog circuit design (GF180MCU process, full flow from SPICE simulation to tapeout), with qualifying designs submittable for fabrication via an MPW program.
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