Dev deep-dive on CUDA instruction latency: atomic ops are variable-latency at the ISA model level
mike64_t · x · 2026-11-01
- mike64t refines the debate with Goldberg: once you issue memory instructions like LDG.E or ATOMG.ADD, timing is undefined from the ISA model's perspective — but observed latencies remain explainable.
- He accepts a "big blob" abstraction to explain behavior but rejects the claim that drivers patch instruction counts; cubins aren't patched post-Kepler anyway. Variable latency of atomic adds is inherent to the ISA model.
Related event: GPU Experts Debate Whether Driver Versions Break CUDA Atomic Determinism(9 posts)→
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