How NVIDIA's instruction scheduling model works: static latencies and scoreboards
mike64_t · x · 2026-11-01
A deep-dive into NVIDIA's instruction scheduling model: IADD sits on the integer pipe with a fixed, knowable latency that ptxas actively asserts on—every cubin in existence relies on it, changing only across SM versions. The whole scheduling model rests on static latencies for certain pipes. Yet some instructions have dynamic latencies: main-memory access triggers long scoreboard stalls or lg throttle behavior, which is exactly why the scoreboard exists—a purely static scheduler can't accommodate dynamic latencies. Codegen doesn't always wait via the scoreboard; it sometimes chooses stalls to guarantee readiness by issue time per the static schedule.
More from Infra
- Reddit bench: EPYC + multi-3090 rig runs Qwen Q8 at 94 tok/s with near-linear scaling to 8 streams — sleight42 · 2026-11-01
- RAM up 7x to $429 in 18 months as Sam Altman says the invisible hand is failing — aakashgupta · 2026-11-01
- Blogger estimates xAI on track for $100B ARR by end-2026 as datacenter builds move up — mitchdeg · 2026-11-01
- Depth-growing 3B models beat dense training on GSM8K (19% vs 12%) while saving 26% pretraining compute — burny_tech · 2026-11-01
- From-scratch CUDA engine runs full GLM-5.3 on 3-6 DGX Sparks; steering vectors flip output language — burny_tech · 2026-11-01
- Picked up a $1,100 RTX 3090 FTW3 for a headless local LLM server — seeking configs — NighthawkXL · 2026-11-01