Qwenputer: developer compiles a 32-bit RISC-V CPU into Qwen's weights, runs C and MicroPython
teortaxesTex · x · 2026-10-28
A Qwen developer ambassador built "Qwenputer": using Qwen's Gated DeltaNet state as RAM, a 32-bit RISC-V CPU is compiled directly into the model's weights, so the model executes instructions internally rather than predicting answers — and can run C and MicroPython programs.
Key details:
- No training involved: a compiler sets every weight directly, turning CPU circuit steps ("read register", "add", "jump if zero") into transformer-layer components — attention heads look things up, feed-forward units do arithmetic, DeltaNet heads hold RAM.
- Each instruction becomes a few generated tokens (ADDR, VAL, STEP); the token stream is the CPU's execution trace, so the CPU genuinely runs as Qwen decodes.
- The RV32IM core (plus Zba extension and a bignum unit) occupies 11 of Qwen's 32 layers, passes official riscv-tests, matches qemu, and free-ran 18 million instructions without a single error.
- Accuracy on one arithmetic benchmark jumped from 48.6% to 100%. Not Linux-class yet, but implements the full RV32IM instruction set.
teortaxesTex comments that the real interpretability triumph would be a generalized data+training method that lets modular "computers" form inside models naturally.
Related event: Qwenputer: A RISC-V CPU Compiled Into Qwen Model Weights(3 posts)→
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