2,100+ tok/s/user for DeepSeek V4.1 Flash on 8× AMD MI355X, 2.8x faster than open-source

JiaZhihao · x · 2026-10-28

An engineering deep-dive on low-latency LLM inference on AMD MI355X: three architectural challenges create coordination overhead — no PDL-equivalent in HIP to overlap dependent kernels, distributed L2 caches adding inter-die traffic, and no NVSwitch-style in-network reductions causing up to 4x more inter-GPU communication. The team co-designed inference engine, kernels, and compiler to tackle this 'coordination tax', reaching 2,100+ tokens/s/user for DeepSeek V4.1 Flash at full quality on 8× MI355X — 2.8x faster than existing open-source solutions — with roofline analysis pointing to further headroom.

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