SLC NAND for AI may need 2% more wafer capacity per 1% share shift, echoing HBM
toptickcrypto · x · 2026-10-26
Citing Lam Research CEO Tim Archer's October 21, 2026 earnings call: growing adoption of SLC NAND for AI could squeeze wafer supply the way HBM did for DRAM. Moving from TLC to SLC-class products cuts bits per cell to roughly one-third, so every 1-percentage-point increase in SLC's share of total NAND bits requires about 2% more wafer capacity to meet the same bit demand. The author argues flash memory could see its own AI-driven wafer trade ratio squeeze if SLC NAND hits.
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