Pat Gelsinger on AI chips: 3 months to design, 9 months to rack — manufacturing is the bottleneck
garrytan · x · 2026-10-10
Former Intel CEO Pat Gelsinger joined a16z's Raghu Raghuram and Guido Appenzeller to discuss the next wave of semiconductor innovation and the physical constraints shaping the AI buildout:
- Designing the 386/486 required inventing your own tools — Gelsinger wrote his own hardware description language, and his team built a compiler and automated placement/routing tools.
- "Nothing's a chip anymore, it's a rack": a clever AI accelerator design might take 3 months, but fabrication, packaging, and racking add 9 more — during which the models it serves keep evolving.
- Real bottlenecks are manufacturing, memory bandwidth, advanced packaging, and power; faster design alone won't fix them.
- They also cover consolidation of specialized AI chips toward fewer architectures, new memory technologies, and copper-to-optical networking.
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