Only 5% of chips tape out right first time — repeat spins, not fabs, may bottleneck custom silicon
ai · x · 2026-10-05
Reposting Nojan Sheybani's take: the common worry that faster chip design will overwhelm fabs misses a key variable — first-pass silicon success. Siemens' 2026 study found only 5% of IC/ASIC respondents achieved first-silicon success. As custom silicon proliferates, repeat tapeouts could become the real capacity bottleneck. If AI design tools also improve first-pass success, fewer respins per successful design would absorb much of the added prototyping demand — and not every chip needs a 2nm TSMC node anyway.
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