DataScalar: The Failed 90s Memory-Centric Architecture That Aged Well
lauriewired · x · 2026-10-02
Security researcher lauriewired argues some of the best CS ideas come from failed late-90s research, spotlighting DataScalar — a memory-centric execution model that traded excess CPU cycles for reduced data movement.
DataScalar ran redundant, sequential copies of a program across processors; the CPU that 'won' the race to needed memory one-way broadcast results, avoiding conventional remote requests — essentially racing threads against each other instead of building a better prefetcher, a odd form of near-data processing. Its risky bet: arithmetic would become virtually free compared to data movement, a call lauriewired says was right.
She notes redundant processing today is mostly used for lockstep safety (aerospace) rather than latency-sensitive performance, and draws a parallel to the data racing in her TailSlayer project to reduce RAM refresh latency stalls.
Related event: Researcher Revives 1990s DataScalar as a Vision for the AI Era(2 posts)→
More from Infra
- PyTorch ships TorchTPU: vLLM and SGLang now run natively on Google TPUs — PyTorch · 2026-10-02
- Lightmatter CEO on Optical Interconnect: NPO Stays, Lasers Move to 300mm Silicon CMOS — BenBajarin · 2026-10-02
- Musk: SpaceX version of VR72 may run at close to 250kW average power with Nvidia — McDonaghMatthew · 2026-10-02
- DDR5/PCIe5 is 15-20% faster for LLM pre-training, but DDR4 wins on cost per dollar — Any-Winter-4079 · 2026-10-02
- Modal makes GPU clusters generally available with one-line RDMA support — josh_wills · 2026-10-02
- Bet on bits, not history: why AI broke the old memory valuation cycle — BenBajarin · 2026-10-02