GaN HEMT + InP HBT monolithically on wafer-scale CMOS: only defense contractors can do it
jwt0625 · x · 2026-09-29
A deep dive into heterogeneous semiconductor integration: only major defense contractors combine GaN HEMTs and InP HBTs with wafer-scale CMOS — foundries each own just one piece (TSMC has GaN, Intel has InP).
Key details: GaN faces up so heat spreads through its SiC substrate before sinking into the Si CMOS chip; InP faces down for high-speed interconnects; 15um-pitch Au-Au thermal compression bonding; DARPA-funded. The real bottlenecks are turnaround time and process step count. Two references included (Gutierrez-Aitken 2017; Sengupta 2024 on Northrop Grumman's Microelectronics Center).
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