Engineer argues HBM stacks dilute bandwidth to 20% of a single DRAM layer
knowrohit07 · x · 2026-09-25
An engineer makes a contrarian case that HBM is the wrong path: a single DRAM layer has 20 TB/cm² of internal bandwidth (derivable from refresh calculations), but stacking 20 layers dilutes average bandwidth to 4 TB/cm² — just 20% of one layer, slower than DDR5. He questions why SK Hynix and Samsung prioritize height over speed, suggesting cheaper memory could be intelligently placed around the stack instead. The quoted thread also covers why high-NA EUV may hit memory before logic, since DRAM's 1T1C cell is a simpler lithography problem than gate-all-around FETs.
Related event: Engineer Questions HBM Stacking: Bandwidth Diluted to 20% at 20 Layers(4 posts)→
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