SonicRV: A Browser-Based Simulator and Visualizer for RISC-V Processor Architectures
blaizedsouza · x · 2026-09-20
JKU researchers released SonicRV, a fully browser-based educational platform for simulating and visualizing RISC-V processor architectures, based on the Harris textbook and used in JKU's computer architecture course (published in IEEE Access).
Features:
- RISC-V assembly editor with syntax highlighting and step-by-step debugger
- Integrated simulator (GHDL) for single-cycle, multicycle and pipelined processors
- Processor-agnostic design accepting any RISC-V core
- Interactive block diagrams with live annotations
- Embedded Surfer waveform viewer for execution traces
- Architectural state (registers/memory) viewable at any point
Note: simulated programs are not persistent.
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