Jeff Dean: RL-accelerated chip design could cut cycles from 150 people and 2 years to 10 in 3 months
haider1 · x · 2026-09-19
Jeff Dean says that if chip design loops are sped up enough for RL to search them, the entire design cycle can be compressed — 10 people in 3 months instead of 150 people and 2 years. That implies more specialized hardware and shorter compute bets, shrinking from 2-6 years to 6 months-4 years.
More from Infra
- Malaysia poised to become a compute superpower with both US and Chinese chips by next year — basedjensen · 2026-11-04
- ByteDance details USDB storage system: 85.8% lower write latency for recommender sequences — _reachsumit · 2026-11-04
- Oracle cancels $7B chip leasing deal with Tencent, FT reports — SumitGup · 2026-11-04
- Inference engine shrunk to 1023 bytes, still runs SmolLM2-135M — cneuralnetwork · 2026-11-04
- Where Residential Proxy IPs Come From: AMA with Massive's CEO — Dylan-Hayes · 2026-11-04
- Musk says space data centers are 'looking pretty appealing right now' — elonmusk · 2026-11-04