Samsung unveils zHBM prototype at FMS 2026: HBM stacked on AI accelerators for up to 8x bandwidth
Kyrannio · x · 2026-09-14
Samsung showcased mockups of zHBM and zNAND-O, plus 400-plus-layer V10 BV-NAND, at FMS 2026 in California.
- zHBM architecture: vertically stacks HBM on top of AI accelerators (xPUs) along the z-axis, minimizing data travel distance to boost bandwidth and power efficiency — Samsung claims up to 8x performance versus conventional layouts, targeting large-scale AI training and inference.
- Context: traditional designs place HBM around the processor; the new approach moves to wide-bus, on-package low-latency designs. Samsung aims to strengthen its position in the fast-growing AI memory market.
- Epic CEO Tim Sweeney amplified the news, calling the evolution of flash toward HBM-like high bandwidth and on-package low latency exciting.
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