AI Designs Frontier Chip Accelerator in Two Weeks with Full RTL and Verification
dair_ai · x · 2026-08-29
New research demonstrates an AI system that designed and deployed a frontier accelerator fully autonomously.
- Process: With only a hardware specification written by two human architects, the AI generated the performance model, RTL, UVM verification environments, formal proofs, firmware, and kernels without human intervention.
- Efficiency: The entire process took under two weeks, with every block achieving 95% coverage via commercial EDA tools and hardware-in-the-loop validation.
- Results: The "Redwood" accelerator targets single-batch low-latency inference. Projected on Samsung 8nm, it delivers 1.75x the throughput at 1.9x lower power against a measured Jetson Orin Nano, a 3.4x gain in performance per watt. The FPGA variant runs multi-billion-parameter Llama and Qwen models.
Related event: Architect Labs claims AI designed Redwood chip in just two weeks(2 posts)→
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