Microsoft Maia 200: Eliminates Cache Hierarchy for Software Defined Dataflow
thoefler · x · 2026-08-27
Microsoft published the detailed architecture of Maia 200, its second-generation inference accelerator for trillion-parameter frontier models, now in production on Azure. The most instructive design decision is the removal of the cache hierarchy. The argument is that LLM inference is mostly data-oblivious, allowing compilers to plan memory accesses in advance; caches add unnecessary cost and latency (30-35% area/energy overhead). Maia 200 uses a Software Defined Locally Accessed Dataflow (SDLA) architecture, exposing scratchpads, DMA engines, semaphores, and compute units to software for precise orchestration via C++ control programs.
Related event: Microsoft Details Maia 200 Accelerator, Ditches Cache Hierarchy(2 posts)→
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