ETH Zurich undergrads tape out full ASIC chips with full funding
AccBalanced · x · 2026-08-27
This post highlights ETH Zurich as likely the only place where undergrads can research, design, and tape out a full ASIC. The author shares a binarized ConvNet accelerator they taped out 10 years ago. Despite the arduous process, the university fully funds the foundry tapeout costs. The discussion also touches on the knowledge gap software developers have regarding chip manufacturing workflows, such as emulation and FPGA simulators.
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