Cerebras CA-6 Stacks Wafer-Scale DRAM 3D
beffjezos · x · 2026-08-26
Cerebras revealed the CA-6 architecture, which will 3D stack wafer-scale DRAM directly on top of the compute dies to obliterate the memory wall. Additionally, new ultrafast tiers are launching, offering up to 5k TPA (Tokens Per Second) for 5.6 Sol-class models.
Related event: Cerebras Unveils CS-4 and Plans 3D-Stacked Wafer-Scale DRAM(3 posts)→
More from Infra
- SGLang ships Day-0 support for FLUX 3 Image Klein: 10 reference images, BF16/FP8/NVFP4 variants — ying11231 · 2026-10-16
- NVIDIA's Nemotron 3.5 Super VL hits CoreWeave: 12B-active multimodal MoE at $0.25/M input tokens — wandb · 2026-10-16
- Chip equipment beats bull case: 2026 WFE seen at $153B, $278B by 2030 — BenBajarin · 2026-10-16
- Steam now launches in 5.23s, beating Epic's 5.47s — and vLLM gets roasted for slow startup — AlpinDale · 2026-10-16
- Shadeform to Announce Six New Features on Oct 19: Lower GPU Costs, More Suppliers — _jaydeepkarale · 2026-10-16
- Fastino launches Training API for SFT/RL, claiming 25-85% cost cut vs Tinker — kalyan_kpl · 2026-10-16