CFET Tech Cuts SRAM Area by Up to 55% vs Nanosheet
vitaliychiley · x · 2026-08-24
Complementary Field-Effect Transistor (CFET) technology achieves major static random access memory (SRAM) scaling beyond traditional nanosheet gate-all-around (GAA) devices. By vertically stacking nFET and pFET transistors, this folding eliminates lateral n-to-p separation spaces, reducing 6T-SRAM bitcell area by up to 40% to 55% compared to standard nanosheet or forksheet benchmarks.
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