If AI Ends Compilers, EDA Flows Die: Need for Formal Verification
satnam6502 · x · 2026-08-17
- Core Argument: If Elon Musk is right that AI will translate high-level requirements straight to machine code, the corollary is that the SystemVerilog EDA flow is dead, with specifications moving directly to gates.
- Challenge: Without HDL, there is no human in the loop to trust, necessitating formal specs for design intent and formal verification of AI-generated gates and GDSII layouts.
- Current State: Digital hardware is already well-suited for model checking and theorem proving; the hard part is formalizing analog behavior at the VLSI level, with Lean 4's Mathlib suggested as a starting point.
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